Diseño de arquitecturas eficientes heterogéneas para comunicaciones de banda ancha sobre redes eléctricas

Abstract

In order to establish communication over a power line, the IEEE 1901/2010 standard for Power-Line Communications (PLC) proposes Filter-Bank Multi-Carrier Modulations (FBMC) as medium access technique. However, a disadvantage of communications through the mains is the channel, which contains considerable noise and significant interference. Nevertheless, the use of channel estimation techniques, together with the use of a channel equalizer, allows to obtain a PLC channel model and compensate the unwanted effects introduced by the channel. Nevertheless, this makes the system more complex and it requires a higher computational load, especially in the reception stage where the channel estimation and equalization are made. This thesis presents the design of heterogeneous architectures for broadband PLC communications. Therefore an analysis is carried out about the medium access techniques to be used, as well as the channel estimation and equalization techniques. This analysis describes mathematically each one of the stages that compose the FBMC system, both the transmission and reception stages. Among the channel estimation methods, we have selected those with the lowest computational load, such as estimators based on least squares (LS). On the other hand, among the equalization techniques for multi-carrier systems based on filter banks, we can find the ASCET equalizers, which present an FIR filter architecture to carry out equalization. This equalizer requires that in the reception stage the filter bank system is duplicated, having in parallel both, one for the modulated cosine (CMFB) and the other for the modulated sine (SMFB). FPGA devices can support the computational load of the system. In addition, some SoC integrate an ARM processor together with the FPGA, as the heterogeneous architecture proposed for the devices of the Xilinx Zynq® family. Within the architecture, those parts with higher timing requirements will be implemented in the programmable logic of the device; on the other hand, the parts that present more relaxed timing restrictions will be coded so that they are run in the processor, thus defining the mixed architecture HW/SW. Each one of the blocks, that compose the hardware part of the architecture, will be modelled using high-level synthesis tools (HLS). On the other hand, in order to obtain an efficient consumption of hardware resources, a datapath study is carried out to adjust the word width to the DSP blocks of the device. In relation to the software parts of the architecture, the acceleration methods available in the device will be described. It should be noted that the unit vector NEON is used to accelerate certain complex calculations, such as FFT. In addition, the software implementation is extended to use all available processor cores for further acceleration. This is done for Zynq® 7000 devices with one and two cores, and for Zynq® UltraScale+ devices with one, two and four cores, establishing inter-core communication mechanisms for both.